annapmicro.com

skintigh.tripod.com

Seth Kintigh's Résumé

http://skintigh.tripod.com/personal/resume.html

To dance like it hurts, love like I need money, and work when people are watching. To crush my enemies, to see them driven before me, and to hear the lamentations of the women. I want to be paid to watch tv. Electrical Engineering (I'm done! Overall GPA: 3.64 (WPI: 3.88, In-house: 3.00). Engineering Leadership Development Program (Aug. 98 - ). Design, simulation and testing of VHDL for the F-22. Developed a 3D missile fly-through simulation on an Alpha platform to be ported to a parallel RTS machine.

fpga-dsp-scratch.blogspot.com

FPGA and DSP from scratch: Critical Path

http://fpga-dsp-scratch.blogspot.com/2008/10/critical-path.html

FPGA and DSP from scratch. Learning accelerated computing and digital signal processing from the very beginning. Saturday, October 4, 2008. During analysis of static timing, the delay from each input to each output of all devices is computed. The delays are then added up along each path through the circuit to get the critical path through the design. The fastest design speed is therefore obtained. The critical path is an approach to logic optimization. Subscribe to: Post Comments (Atom). Maximum combinat...

fpga-site.com

FPGA, EPLD, CPLD Boards

http://www.fpga-site.com/boards.html

FPGA, CPLD, Reconfigurable Computing). Do you have any comments on the following products? Please let other designers know how these products worked for you by sending a message to our Feedback. Form Comments that include a name and a verified return address may be posted for other users. No advertising fees are charged for the following listings. They are provided as a public service by OptiMagic. AEE Engenharia Eletrônica. 8K to 32K EEPROM. 8K to 32K EEPROM. Alcatel (Access Systems Division). 4Mx32 EDO...

fpga-dsp-scratch.blogspot.com

FPGA and DSP from scratch: Timing Summary: Minimum input arrival time before clock

http://fpga-dsp-scratch.blogspot.com/2008/10/timing-summary-minimum-input-arrival.html

FPGA and DSP from scratch. Learning accelerated computing and digital signal processing from the very beginning. Saturday, October 4, 2008. Timing Summary: Minimum input arrival time before clock. The second domain in the Timing Summary (Design Summary, Synthesis Report) is the Minimum input arrival time before clock. Based on Xilinx toolbox. It is the maximum path from the sequential elements to all primary outputs. Again, Gabor. Has a very good explanation on this one. Click here to get to the source.

fpga-dsp-scratch.blogspot.com

FPGA and DSP from scratch: October 2008

http://fpga-dsp-scratch.blogspot.com/2008_10_01_archive.html

FPGA and DSP from scratch. Learning accelerated computing and digital signal processing from the very beginning. Saturday, October 4, 2008. Timing Summary: Maximum output required time after clock. The remaining timing path domain is the Maximum output required time after clock. According to Xilinx toolbox. It is the maximum path from inputs to outputs. Gabor. From Xilinx forums has a concise explanation on this. Links to this post. Maximum output required time before clock. Based on Xilinx toolbox.

fpga-dsp-scratch.blogspot.com

FPGA and DSP from scratch: Timing Summary: Minimum Period

http://fpga-dsp-scratch.blogspot.com/2008/10/timing-summary-minimum-period.html

FPGA and DSP from scratch. Learning accelerated computing and digital signal processing from the very beginning. Saturday, October 4, 2008. Timing Summary: Minimum Period. The first item in the list is the Minimum period, one of the domains of timing paths. According to Xilinx toolbox. It is the maximum path from all primary inputs to the sequential elements. One good explanation is given by, again, gszakacs. In a Xilinx forum. You may want to visit that forum. Subscribe to: Post Comments (Atom). Serial ...

fpga-dsp-scratch.blogspot.com

FPGA and DSP from scratch: July 2008

http://fpga-dsp-scratch.blogspot.com/2008_07_01_archive.html

FPGA and DSP from scratch. Learning accelerated computing and digital signal processing from the very beginning. Thursday, July 24, 2008. VHDL Part 3 : Xilinx ISE tutorial. Note: Click on a picture for clearer view.). 1) Open Xilinx ISE Project Navigator by double clicking its icon on your desktop or go to. Start Programs Xilinx ISE #.#i Project Navigator. Please note that #.#i i. S the version that is installed. You may also type ise from the run command. The New Project Wizard appears. Enable Enhanced ...

fpga-dsp-scratch.blogspot.com

FPGA and DSP from scratch: Writing techware documentation

http://fpga-dsp-scratch.blogspot.com/2008/09/writing-techware-documentation.html

FPGA and DSP from scratch. Learning accelerated computing and digital signal processing from the very beginning. Monday, September 29, 2008. I don't know how to start with this so I need at least a reference. I want a book that will give me just what I need. I don't want to spend too much time in writing. I want to practice coding. So I checked  amazon. 160;for a guide to writing with good reviews. I saw " Writing for Computer Science. By Justin Zobel has excellent reviews (5 reviews only :) . VHDL Part ...

fpga-dsp-scratch.blogspot.com

FPGA and DSP from scratch: Maximum combinational path delay: No path found

http://fpga-dsp-scratch.blogspot.com/2008/10/maximum-combinational-path-delay-no.html

FPGA and DSP from scratch. Learning accelerated computing and digital signal processing from the very beginning. Saturday, October 4, 2008. Maximum combinational path delay: No path found. In the Design Summary, under Synthesis Report (Timing Summary heading), I always see this list:. Minimum input arrival time before clock:. Maximum output required time after clock:. Maximum combinational path delay:. The last item interests me most (among the four) since it sometimes gives me this:. 8220;it is impossib...