cctbio.ece.umn.edu
John Backes - Mediawiki
http://cctbio.ece.umn.edu/wiki/index.php/John_Backes
I completed my Ph.D. under Prof. Marc Riedel. In 2013. My research pertained to logic synthesis, technology mapping, SAT-based algorithms, and model checking. I am now a Senior Research Scientist at Rockwell Collins. Algorithms and Data Structures For Logic Synthesis And Verification Using Boolean Satisfiability. PhD, Electrical and Computer Engineering. The Synthesis of Cyclic Dependencies with Boolean Satisfiability. ACM Transactions on Design Automation of Electronic Systems. Grenoble, France, 2013.
islped.org
ISLPED-2008 Homepage
http://islped.org/X2008
On Low Power Electronics and Design 2008. National Science Seminar Complex, Indian Institute of Science. August 11-13, 2008. The International Symposium on Low Power Electronics and Design. ISLPED) is the premier forum for presentation of recent advances in all aspects of low power design and technologies, ranging from process and circuit technologies, to simulation and synthesis tools, to system level design and optimization. Slides for Keynotes and Tutorials. This symposium is co-hosted by.
brej.org
Charlie's Papers and Publications
http://www.brej.org/papers
A MIPS R3000 microprocessor on an FPGA". Is my third year BSc. project. An Automatic Synchronous to Asynchronous Circuit Convertor". Presented on Monday, 17th of December 2001 at the. 11th UK Asynchronous Forum. Early Output logic using Anti-Tokens". Presented on Tuesday, 17th of December 2002 at the. 13th UK Asynchronous Forum. Asynchronous Early Output and Early Acknowledge Dual-Rail Protocols". Obtaining asynchronous benefits from synchronous design flow". Heraklion, Crete, Greece. A Quasi-Delay-Insen...
alcom.ee.ntu.edu.tw
Welcome to ALCom Lab Website
http://alcom.ee.ntu.edu.tw/links.htm
NTU Graduate Institute of Electronic Engineering. NTU GIEE Electronic Design Automation. Computer Aided Verification, International Conference. Concurrency Theory, International Conference. Design Automation and Test in Europe. Formal Methods in Computer-Aided Design, International Conference. IEEE Symposium on Foundations of Computer Science. International Conference on Computer-Aided Design. International Conference on Computer Design. International Workshop on Logic and Synthesis. Combinatorial Games:...
mriedel.ece.umn.edu
John Backes - Mediawiki
http://www.mriedel.ece.umn.edu/wiki/index.php/John_Backes
I completed my Ph.D. under Prof. Marc Riedel. In 2013. My research pertained to logic synthesis, technology mapping, SAT-based algorithms, and model checking. I am now a Senior Research Scientist at Rockwell Collins. Algorithms and Data Structures For Logic Synthesis And Verification Using Boolean Satisfiability. PhD, Electrical and Computer Engineering. The Synthesis of Cyclic Dependencies with Boolean Satisfiability. ACM Transactions on Design Automation of Electronic Systems. Grenoble, France, 2013.
testplaza.fujiwaralab.net
Calendar - TEST PLAZA
http://testplaza.fujiwaralab.net/en/calendar
Asia and Pacific Regional TTTC, IEEE CS. Asian Test Symposia, IEEE. 10th Asian Test Symposium, ATS'01. 11th Asian Test Symposium, ATS'02. 12th Asian Test Symposium, ATS'03. 13th Asian Test Symposium, ATS'04. 14th Asian Test Symposium, ATS'05. 15th Asian Test Symposium, ATS'06. 16th Asian Test Symposium, ATS'07. 17th Asian Test Symposium, ATS'08. 18th Asian Test Symposium, ATS'09. 19th Asian Test Symposium, ATS'10. 1st Asian Test Symposium, ATS'92. 20th Asian Test Symposium, ATS'11. 9th Workshop on RTL an...
islped.org
ISLPED-2007 Homepage
http://islped.org/X2007
On Low Power Electronics and Design 2007. Portland, Oregon, USA. Embassy Suites Portland Downtown. August 27, Special Session "On the Future of On-Chip Interconnection Architectures (NOCs and Multi-Cores)" by Dr. Shekhar Borkar. Intel) and Dr. William Dally. August 28, Plenary Speech "The Parallel Computing Landscape: A Berkeley View" by Dr. David Patterson. The International Symposium on Low Power Electronics and Design. IEEE Circuits and Systems Society. With technical co-sponsorship from the.
proactive.vt.edu
PROACTIVE
http://www.proactive.vt.edu/download.html
STRATEGATE Sequential ATPG Executable Download. STRATEGATE sequential ATPG download. Automatic Validation Stimuli Generator Executable Download. Automatic Validation Stimuli Generator download. BEACON design validation files. Safety Properties and vectors. General Safety Property Benchmarks. ISCAS85 combinational benchmark circuits. ISCAS89 sequential benchmark circuits. ISCAS93 addendum sequential benchmark circuits. High-level (Verilog) models for ISCAS Circuits. High-level synthesis benchmark circuits.
cctbio.com
John Backes - Mediawiki
http://www.cctbio.com/wiki/index.php/John_Backes
I completed my Ph.D. under Prof. Marc Riedel. In 2013. My research pertained to logic synthesis, technology mapping, SAT-based algorithms, and model checking. I am now a Senior Research Scientist at Rockwell Collins. Algorithms and Data Structures For Logic Synthesis And Verification Using Boolean Satisfiability. PhD, Electrical and Computer Engineering. The Synthesis of Cyclic Dependencies with Boolean Satisfiability. ACM Transactions on Design Automation of Electronic Systems. Grenoble, France, 2013.
cyclify.com
John Backes - Mediawiki
http://www.cyclify.com/wiki/index.php/John_Backes
I completed my Ph.D. under Prof. Marc Riedel. In 2013. My research pertained to logic synthesis, technology mapping, SAT-based algorithms, and model checking. I am now a Senior Research Scientist at Rockwell Collins. Algorithms and Data Structures For Logic Synthesis And Verification Using Boolean Satisfiability. PhD, Electrical and Computer Engineering. The Synthesis of Cyclic Dependencies with Boolean Satisfiability. ACM Transactions on Design Automation of Electronic Systems. Grenoble, France, 2013.
